In some systems, an analog signal is converted to digital samples using an ADC. The frequency and/or phase at which the analog signal is sampled may be “off” and a variety of techniques are used to ensure the digital samples are taken at the proper frequency and/or phase. In one such system, a timing loop is used to adjust the phase and/or frequency of the sampling clock. One drawback to using a timing loop is that a minimum number of samples (cycles) is needed for the timing loop to operate properly. However, this may not be possible in all cases. For example, some applications or systems have a shorter preamble portion (e.g., prior to a payload section) than other applications. It would be desirable to develop techniques that are able to operate robustly in such applications.